In a general dynamic random access memory (DRAM), a memory cell includes one transistor (1T) and one capacitor (1C). Such a 1T1C DRAM is a memory capable of retaining data by accumulating electric charge in a capacitor and thus has no limit on the number of times of writing in principle. As a high-capacity memory device, the DRAM is incorporated in a number of electronic devices because of writing and reading at high speed and a small number of elements in memory cells, which easily enable high integration. The 1T1C DRAM performs data reading in such a manner that electric charge accumulated in the capacitor is released to a bit line and a change in a potential is measured; therefore, the electrostatic capacitance of the capacitor needs to be kept at a certain value or more. As a result, miniaturization of its memory cell makes it more and more difficult to keep necessary electrostatic capacitance.
Besides the 1TC1C memory cell, a memory cell called a gain cell including two or three transistors has been proposed (e.g., Patent Documents 1 and 2). In the gain cell, the amount of electric charge can be amplified by a read transistor and the electric charge can be supplied to a bit line; therefore, it is possible to reduce the capacitance of the capacitor.
A transistor including a metal oxide in a channel formation region (hereinafter, such a transistor may be referred to as an oxide semiconductor transistor or an OS transistor) is known. In addition, a memory in which a write transistor of a gain cell is an OS transistor is proposed (e.g., Patent Document 3 and Non-Patent Documents 1 and 2).
In this specification and the like, a memory which is provided with an OS transistor in a memory cell, as described in Patent Document 3, is referred to as an OS memory.